View AT34C04-14_8347353.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

atmel-8827d-seeprom-at34c04-datasheet_122013 features ? single 1.7v ? 3.6v v cc supply ? jedec jc42.4 (ee1004-v) serial presence detect (spd) compliant ? 2-wire serial interface: i 2 c fast-mode plus (fm+) ? compatible ? 100khz, 400khz, and 1mhz compatibility ? bus timeout supported ? advanced software data protection features ? individually reversible software write protection on all four 128-byte quadrants ? software procedure to verify each quadrant?s write protection status ? 16-byte page write mode ? partial page writes allowed ? self-timed write cycle (5ms maximum) ? schmitt trigger, filtered inputs for noise suppression ? high-reliability ? endurance: 1,000,000 write cycles ? data retention: 100 years ? low operating current ? write ~1.5ma (typical) ? read ~ 0.2ma (typical) ? green packaging options (pb/halide-free/rohs compliant) ? 8-lead jedec soic, 8-lead tssop, and 8-pad udfn at34c04 i 2 c-compatible 4-kbit serial eeprom with reversible software write protection datasheet
at34c04 [datasheet] atmel-8827d-seeprom-at34c04-datasheet_122013 2 table of contents 1. description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2. pin descriptions and pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4. device communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.1 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.2 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.3 acknowledge (ack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.4 no-acknowledge (nack). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.5 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.6 device reset and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.7 timeout function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.8 2-wire software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5. device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6. electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.1 absolute maximum ratings* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7. read and write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.1 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.1.1 set page address and read page address commands . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.2 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.2.1 current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.2.2 random read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.2.3 sequential read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.3 write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.3.1 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.3.2 page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.3.3 acknowledge (ack) polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 7.3.4 write cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8. write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.1 set rswp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.2 clear rswp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.3 read rswp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9. part marking detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.1 part markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 10. ordering code detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 11. at34c04 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 12. package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 12.1 8s1 ? 8-lead jedec soic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 12.2 8x ? 8-lead tssop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 12.3 8ma2 ? 8-pad udfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 13. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
at34c04 [datasheet] atmel-8827d-seeprom-at34c04-datasheet_122013 3 1. description the atmel ? at34c04 is a 1.7v rated minimum operating voltage serial eeprom device containing 4096-bits of serially electrically erasable and programmable read-only memory (eeprom) organized as 512-bytes of eight bits each. the serial eeprom operation is tailored specifically for dram memory modules with serial presence detect (spd) to store a module?s vital product data such as the module?s size, speed, voltage, data width, and timing parameters. the at34c04 is protocol compatible with the legacy jedec ee1002 specification (2-kbit) devices enabling the at34c04 to be utilized in legacy applications without any software changes. the device is designed to respond to specific software commands that allow users to identify and set which half of the memory the internal address counter is located. this special page addressing method to select the upper or lower half of the serial eeprom is what facilitates legacy compatibility. however, there is one exception to the legacy compatibility as the at34c04 does not support the permanent write protection feature. additionally, the at34c04 incorporates a reversible software write protection (rswp) feature enabling the capability to selectively write protect any or all of the four 128-byte quadrants. once the rswp is set, it can only be reversed by sending a specific software command sequence. the at34c04 supports the industry standard 2-wire i 2 c fast-mode plus (fm+) serial interface allowing device communication to operate at up to 1mhz. a bus timeout feature is supported to help prevent system lock-ups. the at34c04 is available in space saving soic, tssop, and udfn packages.
at34c04 [datasheet] atmel-8827d-seeprom-at34c04-datasheet_122013 4 2. pin descriptions and pinouts table 2-1. pin descriptions figure 2-1. pinouts note: 1. the metal pad on the bottom of the udfn package is not internally connected to a voltage potential. this pad can be a ?no connect? or connected to gnd. symbol name and function asserted state type scl serial clock: the scl pin is used to provide a clock to the device and is used to control the flow of data to and from the device. command and input data present on the sda pin is always latched in on the rising edge of scl, while output data on the sda pin is always clocked out on the falling edge of scl. the scl pin must either be forced high when the serial bus is idle or pulled-high using an external pull-up resistor. ? input sda serial data: the sda pin is an open-drain bidirectional input/output pin used to serially transfer data to and from the device. the sda pin must be pulled-high using an external pull-up resistor (not to exceed 8k ? in value) and may be wire-ored with any number of other open-drain or open-collector pins from other devices on the same bus. ? input/ output a 0 , a 1 , a 2 device address inputs: the a 0 , a 1 , and a 2 pins are used to select the device address and corresponds to the three least-significant bits (lsbs) of the i 2 c fm+ seven bit slave address. these pins can be directly connected to v cc or gnd in any combination, allowing up to eight devices on the same bus. the a 0 pin is also an overvoltage tolerant pin, allowing up to 10v to support the reversible software write protection (rswp) feature (see section 8. ). ? input nc no connect: the nc pin is not bonded to a die pad. this pin can be connected to gnd or left floating. ? ? v cc device power supply: the v cc pin is used to supply the source voltage to the device. operations at invalid v cc voltages may produce spurious results and should not be attempted. ? power gnd ground: the ground reference for the power supply. gnd should be connected to the system ground. ? power 8-lead tssop 8-pad udfn bottom view top view top view 8-lead soic 1 2 3 4 8 7 6 5 a 0 a 1 a 2 gnd v cc nc scl sda 1 2 3 4 8 7 6 5 a 0 a 1 a 2 gnd v cc nc scl sda a 0 a 1 a 2 gnd v cc nc scl sda 1 2 3 4 8 7 6 5 (1)
at34c04 [datasheet] atmel-8827d-seeprom-at34c04-datasheet_122013 5 3. block diagram 1 page start stop detector gnd a 2 memory system control module high voltage generation circuit data & ack input/output control address register and counter software write protection control d out d in hardware address comparator v cc scl sda power on reset generator 4-kbit eeprom array column decoder row decoder data register a 1 a 0 quadrant 0 quadrant 1 quadrant 2 quadrant 3
at34c04 [datasheet] atmel-8827d-seeprom-at34c04-datasheet_122013 6 4. device communication the at34c04 operates as a slave device and utilizes a simple 2-wire digital serial interface, compatible with the i 2 c fast-mode plus (i 2 c fm+) protocol, to communicate with a host controller, commonly referred to as the bus master. the master initiates and controls all read and write operations to the slave devices on the serial bus, and both the master and the slave devices can transmit and receive data on the bus. the serial interface is comprised of just two signal lines: the serial clock (scl) and the serial data (sda). the scl pin is used to receive the clock signal from the master, while the bidirectional sda pin is used to receive command and data information from the master, as well as, to send data back to the master. data is always latched into the at34c04 on the rising edge of scl and is always output from the device on the falling edge of scl. both the scl and sda pin incorporate integrated spike suppression filters and schmitt triggers to minimize the effects of input spikes and bus noise. all command and data information is transferred with the most-significant bit (msb) first. during the bus communication, one data bit is transmitted every clock cycle, and after eight bits (one byte) of data has been transferred, the receiving device must respond with either an acknowledge (ack) or a no-acknowledge (nack) response bit during a ninth clock cycle (ack/nack clock cycle) generated by the master. therefore, nine clock cycles are required for every one byte of data transferred. there are no unused clock cycles during any read or write operation so there must not be any interruptions or breaks in the data stream during each data byte transfer and ack or nack clock cycle. during data transfers, data on the sda pin must only change while scl is low, and the data must remain stable while scl is high. if data on the sda pin changes while scl is high, then either a start or a stop condition will occur. start and stop conditions are used to initiate and end all serial bus communication between the master and the slave devices.the number of data bytes transferred between a start and a stop condition is not limited and is determined by the master. in order for the serial bus to be idle, both the scl and sda pins must be in the logic 1 state at the same time. 4.1 start condition a start condition occurs when there is a high-to-low transition on the sda pin while the scl pin is stable in the logic 1 state. the master uses a start condition to initiate any data transfer sequence, therefore the start condition must precede any command. the at34c04 will continuously monitor the sda and scl pins for a start condition, and the device will not respond unless one is given. please refer to figure 4-1 on page 7 for more details. 4.2 stop condition a stop condition occurs when there is a low-to-high transition on the sda pin while the scl pin is stable in the logic 1 state. the master uses the stop condition to end a data transfer sequence to the at34c04 which will subsequently return to the idle state. the master can also utilize a repeated start condition instead of a stop condition to end the current data transfer if the master will perform another operation. please refer to figure 4-1 on page 7 for more details.
at34c04 [datasheet] atmel-8827d-seeprom-at34c04-datasheet_122013 7 4.3 acknowledge (ack) after every byte of data is received, the at34c04 must acknowledge to the master that it has successfully received the data byte by responding with an ack. this is accomplished by the master first releasing the sda line and providing the ack/nack clock cycle (a ninth clock cycle for every byte). during the ack/nack clock cycle, the at34c04 must output a logic 0 (ack) for the entire clock cycle such that the sda line must be stable in the logic 0 state during the entire high period of the clock cycle. please refer to figure 4-1 on page 7 for more details. 4.4 no-acknowledge (nack) when the at34c04 is transmitting data to the master, the master can indicate that it is done receiving data and wants to end the operation by sending a nack response to the at34c04 instead of an ack response. this is accomplished by the master outputting a logic 1 during the ack/nack clock cycle, at which point the at34c04 will release the sda line so that the master can then generate a stop condition. in addition, the at34c04 can use a nack to respond to the master instead of an ack for certain invalid operation cases such as an attempt to write to a read-only register. figure 4-1. start, stop, and ack 4.5 standby mode the at34c04 incorporates a low-power standby mode which is enabled: ? upon power-up or ? after the receipt of a stop condition and the completion of any internal operations. scl sda sda must be stable sda change allowed sda change allowed acknowledge valid stop condition start condition 12 89 sda must be stable acknowledge window the transmitting device (master or slave) must release the sda line at this point to allow the receiving device (master or slave) to drive the sda line low to ack the previous 8-bit word. the receiver (master or slave) must release the sda line at this point to allow the transmitter to continue sending new data.
at34c04 [datasheet] atmel-8827d-seeprom-at34c04-datasheet_122013 8 4.6 device reset and initialization the at34c04 incorporates an internal power-on reset (por) circuit to help prevent inadvertent operations during power-up and power down cycles. on a cold power-up, the supply voltage must rise monotonically between v por(max) and v cc(min) without any ring back to ensure a proper power-up (see figure 4-2 ). once the supply voltage has passed the v por(min) threshold, the device internal reset process is initiated. completion of the internal reset process occurs within the t init time listed in table 4-1 . before selecting the device and issuing protocol, a valid and stable supply voltage must be applied and no protocol should be issued to the device for the time specified by the t init parameter. the supply voltage must remain stable and valid until the end of the protocol transmission, and for a write instruction, until the end of the internal write cycle. figure 4-2. power-up timing table 4-1. power-up conditions symbol parameter min max units t por power-on reset time 10.0 ms v por power-on reset voltage range 1.0 1.6 v t init time from power-on to first command 10.0 ms t poff warm power cycle off time 1.0 ms do not attempt device access during this time v cc cold power-on reset warm power-on reset v por (max) v cc (min) time t poff t init t por device access permitted v por (min)
at34c04 [datasheet] atmel-8827d-seeprom-at34c04-datasheet_122013 9 4.7 timeout function the at34c04 supports the industry standard bus timeout feature to help prevent potential system bus hang-ups. the device resets its serial interface and will stop driving the bus (will let sda float high) if the scl pin is held low for more than the minimum timeout (t out ) specification. the at34c04 will be ready to accept a new start condition before the maximum t out has elapsed (see figure 4-3 ). this feature does require a minimum scl clock speed of 10khz to avoid any timeout issues. figure 4-3. timeout 4.8 2-wire software reset after an interruption in protocol, power loss, or system reset, any 2-wire part can be reset by following these steps: 1. create a start condition. 2. clock nine cycles. 3. create another start condition followed by stop condition as shown in figure 4-4 . figure 4-4. 2-wire software reset device will release bus and be ready to accept a new start condition within this time t timeout (max) t timeout (min) scl scl sda 9 8 3 2 1 start condition start condition stop condition dummy clock cycles
at34c04 [datasheet] atmel-8827d-seeprom-at34c04-datasheet_122013 10 5. device addressing the at34c04 requires a 7-bit device address and a read/write select bit following a start condition from the master to initiate communication with the serial eeprom. the device address byte is comprised of a 4-bit device type identifier followed by three device address bits (a2, a1, and a0) and a r/ w bit and is clocked by the master on the sda pin with the most significant bit first (see table 5-1 ). the at34c04 will respond to two unique device type identifiers. the device type identifier of ?1010? (ah) is necessary to select the device for reading or writing. the device type identifier of ?0110? (6h) has multiple purposes. first, it is used to access the page address function which determines what the internal address counter is set to. for more information on accessing the page address function, please refer to section 7.1.1 . the device type identifier of ?0110? (6h) is also used to access the software write protection feature of the device. information on the software write protection functionality can be found in section 8. table 5-1. at34c04 device address byte the software device address bits (a2, a1, and a0) must match their corresponding hard-wired device address inputs (a 2 , a 1 and a 0 ) allowing up to eight devices on the bus at the same time (see table 5-2 ). the eighth bit of the address byte is the r/ w operation selection bit. a read operation is selected if this bit is a logic 1, and a write operation is selected if this bit is a logic 0. upon a compare of the device address byte, the at34c04 will output an ack during the ninth clock cycle; if a compare is not true, the device will output a nack during the ninth clock cycle and return the device to the low-power standby mode. table 5-2. device address combinations bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 function device type identifier device address read/write eeprom read/write 1 0 1 0 a2 a1 a0 r/ w write protection and page address functions 0 1 1 0 a2 a1 a0 r/ w software device address bits hard-wired device address inputs a2, a1, a0 a 2 a 1 a 0 0 0 0 gnd gnd gnd 0 0 1 gnd gnd v cc 0 1 0 gnd v cc gnd 0 1 1 gnd v cc v cc 1 0 0 v cc gnd gnd 1 0 1 v cc gnd v cc 1 1 0 v cc v cc gnd 1 1 1 v cc v cc v cc
at34c04 [datasheet] atmel-8827d-seeprom-at34c04-datasheet_122013 11 6. electrical specifications 6.1 absolute maximum ratings* table 6-1. dc characteristics note: 1. v il min and v ih max are reference only and are not tested. temperature under bias . . . . . . . . . . -40c to +125c storage temperature . . . . . . . . . . . . -65c to +150c supply voltage with respect to ground . . . . . . . . . . . . . .-0.5v to +4.3v all other input voltages with respect to ground . . . . . . . . . .-0.5v to v cc + 0.5v all input voltages with respect to ground . . . . . . . . . .-0.5v to v cc + 0.5v *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. functional operation of the device at these ratings or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage extremes referenced in the ?absolute maximum ratings? are intended to accommodate short duration undershoot/overshoot conditions and does not imply or guarantee functional device operation at these levels for any extended period of time. applicable over recommended operating range: t a = ?20c to +125c, v cc = 1.7v to 3.6v (unless otherwise noted). symbol parameter test condition min typ max units v cc supply voltage 1.7 3.6 v i cc1 supply current v cc = 3.6v read at 100khz 0.4 1.0 ma i cc2 supply current v cc = 3.6v write at 100khz 1.5 3.0 ma i sb standby current v cc = 1.7v v in = v cc or v ss 1.6 3.0 a v cc = 3.6v v in = v cc or v ss 1.6 4.0 a i li input leakage current v in = v cc or v ss 0.1 2.0 a i lo output leakage current v out = v cc or v ss 0.1 2.0 a v il input low level (1) -0.5 0.3 * v cc v v ih input high level (1) 0.7 * v cc v cc + 0.5 v v ol1 low-level output voltage open-drain v cc > 2v i ol = 3ma 0.4 v v ol2 v cc 2v i ol = 2ma 0.2 * v cc v i ol low-level output current v ol = 0.4v freq 400khz 3.0 ma v ol = 0.6v freq 400khz 6.0 ma v ol = 0.4v freq > 400khz 20.0 ma v hv a 0 pin high voltage v hv - v cc 4.8v 7 10 v v hyst1 input hysteresis (sda, scl) v cc < 2v 0.10 * v cc v v hyst2 input hysteresis (sda, scl) v cc 2v 0.05 * v cc v
at34c04 [datasheet] atmel-8827d-seeprom-at34c04-datasheet_122013 12 table 6-2. ac characteristics notes: 1. this parameter is ensured by characterization only. 2. the minimum frequency is specified at 10khz to avoid activating the timeout feature. applicable over recommended operating range: t a = ?20c to +125c, v cc = 1.7v to 3.6v, cl = 1 ttl gate and 100 f (unless otherwise noted). symbol parameter v cc < 2.2v v cc 2.2v units 100khz 400khz 1000khz min max min max min max f scl clock frequency, scl 10 (2) 100 10 (2) 400 10 (2) 1000 khz t low clock pulse width low 4700 1300 500 ns t high clock pulse width high 4000 600 260 ns t i noise suppression time 50 50 50 ns t buf time the bus must be free before a new transmission can start (1) 4700 1300 500 ns t hd.sta start hold time 4000 600 260 ns t su.sta start set-up time 4700 600 260 ns t hd.di data in hold time 0.0 0.0 0.0 ns t su.dat data in set-up time 250 100 50 ns t r inputs rise time (1) 1000 20 300 120 ns t f inputs fall time (1) 300 20 300 120 ns t su.sto stop set-up time 4000 600 260 ns t hd.dat data out hold time 200 3450 200 900 0 350 ns t wr write cycle time 5 5 5 ms t out timeout time 25 35 25 35 25 35 ms endurance 25c, page mode (1) 1,000,000 write cycles
at34c04 [datasheet] atmel-8827d-seeprom-at34c04-datasheet_122013 13 figure 6-1. bus timing scl: serial clock, sda: serial data i/o table 6-3. pin capacitance (1) note: 1. this parameter is ensured by characterization only. applicable over recommended operating range from t a = 25c, f = 1 mhz, v cc = 1.7v - 3.6v. symbol test condition max units conditions c i/o input/output capacitance (sda) 8 pf v i/o = 0v c in input capacitance (a 0 , a 1 , a 2 , scl) 6 pf v in = 0v scl sda t f t high t low t low t r t buf t su.sto t su.dat t hd.dat t hd.sta t su.sta
at34c04 [datasheet] atmel-8827d-seeprom-at34c04-datasheet_122013 14 7. read and write operations 7.1 memory organization to provide the greatest flexibility and backwards compatibility with the previous generations of spd devices, the at34c04 memory organization is organized into two independent 2-kbit memory arrays. each 2-kbit (256-byte) section is internally organized into two independent quadrants of 128 bytes with each quadrant comprised of eight pages of 16 bytes. including both memory sections, there are four 128-byte quadrants totaling 512 bytes. the memory array organization details are shown in section 3. on page 5 and table 7-1 . 7.1.1 set page address and read page address commands the at34c04 incorporates an innovative memory addressing technique that utilizes a set page address (spa) and read page address (rpa) commands to select and verify the desired half of the memory enabled to perform write and read operations. due to the requirement for a 0 pin to be driven to v hv , the spa and the rpa commands are fully supported in a single dimm (isolated dimm) end application or a single dimm programming station only. example: if spa = 0, then the first-half or lower 256 bytes of the serial eeprom is selected allowing access to quadrant 0 and quadrant 1. alternately, if spa = 1, then the second-half or upper 256 bytes of the serial eeprom is selected allowing access to quadrant 2 and quadrant 3 . table 7-1. spa setting and memory organization setting the set page address (spa) value selects the desired half of the eeprom for performing write or read operations. this is done by sending the spa as seen in figure 7-1 . the spa command sequence requires the master to transmit a start condition followed by sending a control byte of ?011011*0? where the ?*? in the bit 7 position will dictate which half of the eeprom is being addressed. a ?0? in this position (or 6ch) is required to set the page address to the first half of the memory and a ?1? (or 6eh) is necessary to set the page address to the second half of the memory. after receiving the control byte, the at34c04 should return an ack and the master should follow by sending two data bytes of don?t care values. the at34c04 responds with a nack to each of these two data bytes although the jedec ee1004v specification allows for either an ack or nack response. the protocol is completed by the master sending a stop condition to end the operation. figure 7-1. set page address (spa) block set page address (spa) memory address locations quadrant 0 0 00h to 7fh quadrant 1 80h to ffh quadrant 2 1 00h to 7fh quadrant 3 80h to ffh scl sda start by master ack from slave nack from slave stop by master nack from slave control byte most significant data byte least significant data byte 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 0 1 1 0 1 1 * 0 0 x x x x x x x x 1 x x x x x x x x 1 msb msb msb bit * = 1: indicates the page address is located in the second half of the memory. bit * = 0: indicates the page address is located in the first half of the memory.
at34c04 [datasheet] atmel-8827d-seeprom-at34c04-datasheet_122013 15 reading the state of the spa can be accomplished via the read page address (rpa) command. the master can issue the rpa command to determine if the at34c04?s internal address counter is located in the first 2-kbit section or the second 2-kbit memory section based upon the device?s ack or nack response to the rpa command. the rpa command sequence requires the master to transmit a start bit followed by a control byte of ?01101101? (6dh). if the device?s current address counter (page address) is located in the first half of the memory, the at34c04 responds with an ack to the rpa command. alternatively, a nack response to the rpa command indicates the page address is located in the second half of the memory (see figure 7-2 ). following the control byte and the device?s ack or nack response, the at34c04 should transmit two data bytes of don?t care values. the master should nack on these two data bytes followed by the master sending a stop condition to end the operation. after power-up, the spa is set to zero indicating internal address counter is located in the first half of the memory. performing a software reset (see 2-wire software reset on page 9 ) will also set the spa to zero. the at34c04 incorporates a reversible software write protect (rswp) feature that allows the ability to selectively write protect data stored in any or all of the four 128-byte quadrants. see section 8. ?write protection? on page 21 for more information on the rswp feature. figure 7-2. read page address (rpa) scl sda start by master ack or nack from slave nack from master stop by master nack from master control byte most significant data byte least significant data byte 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 0 1 1 0 1 1 0 1 * x x x x x x x x 1 x x x x x x x x 1 msb msb msb bit * = 1: nack indicates the device?s internal address counter is located in the second half of the memory. bit * = 0: ack indicates the device?s internal address counter is located in the first half of the memory.
at34c04 [datasheet] atmel-8827d-seeprom-at34c04-datasheet_122013 16 7.2 read operations all read operations are initiated by the master transmitting a start bit, a device type identifier of ?1010? (ah), three software address bits (a2, a1, a0) that match their corresponding hard-wired address pins (a 2 , a 1 , a 0 ), and the r/ w select bit with a logic 1 state. in the following clock cycle, the device should respond with an ack. the subsequent protocol depends on the type of read operation desired. there are three read operations: current address read, random address read, and sequential read. caution: all read operations should be preceded by the spa and/or rpa commands to ensure the desired half of the memory is selected. the reason this is important, for example, during a sequential read operation on the last byte in the first half of the memory (address ffh) with spa=0 (indicating first half is selected), the internal address counter will roll-over to address 00h in the first half of memory as opposed to the first byte in the second half of the memory. for more information on the spa and rpa commands, see section 7.1.1 on page 14 . 7.2.1 current address read following a start condition, the master only transmits the device address byte with the r/ w select bit set to a logic 1 (see figure 7-3 ). the at34c04 should respond with an ack and then serially transmits the data word addressed by the internal address counter. the internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. this address stays valid between operations as long as power to the device is maintained. the address roll-over during a read is from the last byte of the last page to the first byte of the first page of the addressed 2-kbit (depends on the current spa setting). to end the command, the master does not respond with an ack but does generate a following stop condition. figure 7-3. current address read 7.2.2 random read a random read operation allows the master to access any memory location in a random manner and requires a dummy write sequence to preload the starting data word address. to perform a random read, the device address byte and the word address byte are transmitted to the at34c04 as part of the dummy write sequence (see figure 7-4 ). once the device address byte and data word address are clocked in and acknowledged by the at34c04, the master must generate another start condition. the master initiates a current address read by sending another device address byte with the r/ w select bit to a logic 1. the at34c04 acknowledges the device address byte, increments its internal address counter and serially clocks out the first data word. the device will continue to transmit sequential data words as long as the master continues to ack each data word. to end the sequence, the master responds with a nack and a stop condition. scl sda device address byte data word (n) start by master ack from slave nack from master stop by master msb msb 1 0 1 0 a2 a1 a0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 1 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
at34c04 [datasheet] atmel-8827d-seeprom-at34c04-datasheet_122013 17 figure 7-4. random read 7.2.3 sequential read a sequential read operation is initiated in the same way as a random read operation, except after the at34c04 transmits the first data word, the master responds with an ack (instead of a nack followed by a stop condition). as long as the at34c04 receives an ack, it will continue to increment the data word address and serially clock out the sequential data words (see figure 7-5 ). when the internal address counter is at the last byte of the last page, the data word address will roll-over to the beginning of the selected 2-kbit array (depending on the spa setting) starting at address zero, and the sequential read operation will continue. the sequential read operation is terminated when the master responds with a nack followed by a stop condition. figure 7-5. sequential read scl sda start by master ack from slave ack from slave device address byte word address byte msb msb 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 1 0 a2 a1 a0 0 0 a7 a6 a5 a4 a3 a2 a1 a0 0 dummy write start by master ack from slave nack from master device address byte data word (n) stop by master msb msb 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 1 0 a2 a1 a0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 1 scl sda start by master ack from slave ack from master device address byte data word (n) msb msb 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 1 0 a2 a1 a0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 0 ack from master nack from master stop by master ack from master data word (n+1) data word (n+2) data word (n+x) 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 d7 d6 d5 d4 d3 d2 d1 d0 0 d7 d6 d5 d4 d3 d2 d1 d0 0 d7 d6 d5 d4 d3 d2 d1 d0 1 msb msb msb
at34c04 [datasheet] atmel-8827d-seeprom-at34c04-datasheet_122013 18 7.3 write operations the at34c04 supports single byte write and page write operations up to the maximum page size of 16 bytes in one operation. the only difference between a byte write and a page write operation is the amount of data bytes sent to the device. regardless of whether a byte write or page write operation is performed, the internally self-timed write cycle will take the same amount of time to write the data to the addressed memory location(s). caution: all byte write and page write operations should be preceded by the spa and or rpa commands to ensure the internal address counter is located in the desired half of the memory. if a byte write or page write operation is attempted to a protected quadrant, the at34c04 will respond (ack or nack) to the write operation according to table 7-2 . table 7-2. acknowledge status when writing data or defining write protection 7.3.1 byte write following the start condition from the master, the device type identifier ( ?1010? ), the device address bits and the r/ w select bit (set to a logic 0) are clocked onto the bus by the master. this indicates to the addressed device that the master will follow by transmitting a byte with the word address. the at34c04 will respond with an ack during the ninth clock cycle. then the next byte transmitted by the master is the 8-bit word address of the byte location to be written into the serial eeprom. after receiving an ack from the at34c04, the master transmits the data word to be programmed followed by an ack from the at34c04. the master ends the write sequence with a stop condition during the 10 th clock cycle to initiate the internally self-timed write cycle. a stop condition issued during any other clock cycle during the write operation will not trigger the internally self-timed write cycle. once the write cycle begins, the pre-loaded data word will be programmed in the amount of time not to exceed the t wr specification. the t wr time is defined in more detail in section 7.3.4 on page 20 . during this time, the master should wait a fixed amount of time set to the t wr specification, or for time sensitive applications, an ack polling routine can be implemented. all inputs are ignored by the device during the write cycle and the device will not respond until the write cycle is complete (see figure 7-9 ). the serial eeprom will increment its internal address counter each time a byte is written. figure 7-6. byte write quadrant status instruction ack word address ack data word ack write cycle write protected with set rswp set rswp nack don?t care nack don?t care nack no clear rswp ack don?t care ack don?t care ack yes byte write or page write to protected quadrant ack word address ack data nack no not protected set rswp or clear rswp ack don?t care ack don?t care ack yes byte write or page write ack word address ack data ack yes scl sda device address byte word address byte data word start by master ack from slave ack from slave msb msb ack from slave stop by master msb 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 1 0 a2 a1 a0 0 0 a7 a6 a5 a4 a3 a2 a1 a0 0 d7 d6 d5 d4 d3 d2 d1 d0 0
at34c04 [datasheet] atmel-8827d-seeprom-at34c04-datasheet_122013 19 7.3.2 page write the 4-kbit serial eeprom is capable of writing up to 16 data bytes at a time executing the page write protocol sequence. a partial or full page write operation is initiated the same as a byte write operation except that the master does not send a stop condition after the first data word is clocked in. instead, after the device has acknowledged receipt of the first data word, the master can transmit up to fifteen more data words. the device will respond with an ack after each data word is received. the master must terminate the page write sequence with a stop condition during the 10th clock cycle (see figure 7-7 ) to start the write cycle. a stop condition issued at any other clock cycle will not initiate the internally self-timed write cycle and the write sequence will have to be repeated again. once the write cycle begins, the data words should be programmed in the amount of time not exceed the t wr parameter (see figure 7-9 ). during this time, the master should wait a fixed amount of time set to the specified t wr parameter, or for time sensitive applications, an acknowledge polling routine can be implemented as described in section 7.3.3 . the t wr time is defined in more detail in section 7.3.4 on page 20 . the lower four bits of the data word address are internally incremented following the receipt of each data word. the higher data word address bits are not incremented, retaining the memory page row location. when the internally generated word address reaches the page boundary, then the following data word is placed at the beginning of the same page. if more than sixteen data words are transmitted to the device, the data word address will roll-over and the previous data will be overwritten. the address roll-over during a write sequence is from the last byte of the current page to the first byte of the same page. figure 7-7. page write scl sda start by master ack from slave ack from slave device address byte word address byte msb msb 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 1 0 a2 a1 a0 0 0 a7 a6 a5 a4 a3 a2 a1 a0 0 ack from slave ack from slave stop by master ack from slave data word (n) data word (n+1) data word (n+15) 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 d7 d6 d5 d4 d3 d2 d1 d0 0 d7 d6 d5 d4 d3 d2 d1 d0 0 d7 d6 d5 d4 d3 d2 d1 d0 0 msb msb msb
at34c04 [datasheet] atmel-8827d-seeprom-at34c04-datasheet_122013 20 7.3.3 acknowledge (ack) polling an ack polling routine can be implemented to optimize time sensitive applications that would not prefer waiting the fixed maximum write cycle time and would prefer to know immediately when the serial eeprom write cycle has completed to start a subsequent operation. once the internally self timed write cycle has started (the stop condition during the 10 th clock cycle at the end of the write sequence), the device inputs are disabled and ack polling can be initiated (see figure 7-8 ). an ack polling routine involves sending a valid start condition followed by the device address byte. while the write cycle is in progress, the device will not respond with an ack indicating the device is busy writing data. once complete, the device will ack and the next device operation can be started. figure 7-8. acknowledge polling flow chart 7.3.4 write cycle timing the length of the self timed write cycle, or t wr , is defined as the amount of time from a valid stop condition that begins the internal write sequence to the start condition of the first device address byte sent to the at34c04 that it subsequently responds to with an ack. figure 7-9 has been included to show this measurement. figure 7-9. write cycle timing scl: serial clock, sda: serial data i/o did the device ack? send any write protocol send stop condition to initiate write cycle send start condition followed by valid device address byte continue to next operation no yes t wr stop condition start condition data word n ack d0 sda stop condition scl 89 ack first acknowledge from the device to a valid device address sequence after write cycle is initiated. the minumum t wr can only be determined through the use of an ack polling routine. 9
at34c04 [datasheet] atmel-8827d-seeprom-at34c04-datasheet_122013 21 8. write protection the at34c04 incorporates a reversible software write protection (rswp) feature that allows the ability to selectively write protect data stored in each of the four independent 128-byte eeprom quadrants. table 8-1 identifies the memory quadrant identifier with its associated quadrant, spa and memory address locations. the at34c04 has three rswp software commands: ? set rswp command for setting the rswp. ? clear rswp command for resetting all of the quadrants to an unprotected state. ? read rswp command for checking the rswp status. table 8-1. memory organization 8.1 set rswp setting the rswp is enabled by sending the set rswp command, similar to a normal write command to the device which programs the write protection to the target quadrant. the set rswp sequence requires sending a control byte of ?0110mmm0? (where ?m? represents the memory quadrant identifier for the target quadrant to be write-protected) with the r/ w bit set to a logic 0. in conjunction with sending the protocol, the a 0 pin must be connected to v hv for the duration of the rswp sequence (see figure 8-1 ). the set rswp command acts on a single quadrant only as specified in the set rswp command and can only be reversed by issuing the clear rswp command and will unprotect all quadrants in one operation (see table 8-2 ). example: if quadrant 0 and quadrant 3 are to be write-protected, two separate set rswp commands would be required; however, only one clear rswp command is needed to clear and unprotect both quadrants. table 8-2. set rswp and clear rswp notes: 1. x = don?t care but recommended to be hard-wired to v cc or gnd. 2. see table 6-1 for v hv value. 3. due to the requirement for the a 0 pin to be driven to v hv , the rswp set and rswp clear commands are fully supported in a single dimm (isolated dimm) end application or a single dimm programming station only. block spa address locations memory quadrant identifier quadrant 0 0 00h to 7fh 001 quadrant 1 0 80h to ffh 100 quadrant 2 1 00h to 7fh 101 quadrant 3 1 80h to ffh 000 function control byte pin device type identifier memory quadrant identifier r/ w a 2 a 1 a 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 set rswp, quadrant 0 x x v hv 0 1 1 0 0 0 1 0 set rswp, quadrant 1 x x 1 0 0 0 set rswp, quadrant 2 x x 1 0 1 0 set rswp, quadrant 3 x x 0 0 0 0 clear rswp x x 0 1 1 0
at34c04 [datasheet] atmel-8827d-seeprom-at34c04-datasheet_122013 22 figure 8-1. set rswp and clear rswp 8.2 clear rswp similar to the set rswp command, the reversible write protection on all quadrants can be reversed or unprotected by transmitting the clear rswp command. the clear rswp sequence requires the master to send a start condition followed by sending a control byte of ?01100110? (66h) with the r/ w bit set to a logic 0. the at34c04 should respond with an ack. the master transmits a word address byte and data bytes with don?t care values. the at34c04 will respond with either an ack or nack to both the word address and data word. in conjunction with sending the protocol, the a 0 pin must be connected to v hv for the duration of the clear rswp command (see figure 8-1 ). to end the clear rswp sequence, the master sends a stop condition. caution: the write protection of individual quadrants cannot be reversed separately, and executing the clear rswp command will clear the write protection on all four quadrants leaving all quadrants with no software write protection. 8.3 read rswp the read rswp command allows the ability to check a quadrant?s write protection status. to find out if the software write protection has been set to a specific quadrant, the same procedure that was used to set the quadrant?s write protection can be utilized except that the r/ w select bit is set to a logic 1, and the a 0 pin is not required to have v hv (see table 8-4 ). the read rswp sequence requires sending a control byte of ?0110mmm1? (where the ?m? represents the memory quadrant identifier for the quadrant to be read) with the r/ w bit set to a logic 1 (see figure 8-2 ). if the rswp has not been set, then the at34c04 responds to the control byte with an ack. if the rswp has been set, the at34c04 responds with a nack. in either case, both word address and data word bytes will not be acknowledged. the operation is completed by the master creating a stop condition. a summary of the response is shown in table 8-3 . table 8-3. acknowledge when reading protection status scl sda start by master ack from slave ack or nack from slave stop by master ack or nack from slave control byte word address byte data word 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 0 1 1 0 m m m 0 0 x x x x x x x x 0/1 x x x x x x x x 0/1 msb msb msb x = don?t care m = memory quadrant identifier quadrant status instruction sent instruction response word address sent word address response data word sent data word response write protected read rswp nack don?t care nack don?t care nack not protected read rswp ack don?t care nack don?t care nack
at34c04 [datasheet] atmel-8827d-seeprom-at34c04-datasheet_122013 23 table 8-4. read rswp note: 1. x = don?t care but recommend to be hard-wired to v cc or gnd. figure 8-2. read rswp function pin control byte device type identifier memory quadrant identifier r/ w a 2 a 1 a 0 b7 b6 b5 b4 b3 b2 b1 b0 read rswp, quadrant 0 x x 0, 1 or v hv 0 1 1 0 0 0 1 1 read rswp, quadrant 1 x x 1 0 0 1 read rswp, quadrant 2 x x 1 0 1 1 read rswp, quadrant 3 x x 0 0 0 1 sck sda start by master ack or nack from slave nack from master stop by master nack from master control byte word address byte data byte 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 0 1 1 0 m m m 1 0/1 x x x x x x x x 1 x x x x x x x x 1 msb msb msb x = don?t care m = memory quadrant identifier
at34c04 [datasheet] atmel-8827d-seeprom-at34c04-datasheet_122013 24 9. part marking detail 9.1 part markings drawing no. rev. title catalog number truncation at34c04 truncation code ##: 44 aaaaaaaa 44 m @ atml5yww 8-lead soic 8-lead tssop aaaaaaa 44 m @ at5yww 8-lead udfn 44 5m@ yxx 2.0 x 3.0 mm body note 2: package drawings are not to scale note 1: designates pin 1 package drawing contact: packagedrawings@atmel.com 34c04sm b 8/16/12 34c04sm, at34c04 package marking information date codes voltages y = year m = month ww = work week of assembly m: 1.7v min 2: 2012 6: 2016 a: january 02: week 2 3: 2013 7: 2017 b: february 04: week 4 4: 2014 8: 2018 ... ... 5: 2015 9: 2019 l: december 52: week 52 country of assembly lot number grade/lead finish material @ = country of assembly aaa...a = atmel wafer lot number 5: industrial (c) (-20c to 125c)/nipdau trace code atmel truncation xx = trace code (atmel lot numbers correspond to code) at: atmel example: aa, ab.... yz, zz atm: atmel atml: atmel at34c04: package marking information
at34c04 [datasheet] atmel-8827d-seeprom-at34c04-datasheet_122013 25 10. ordering code detail 11. at34c04 ordering information additional package types that are not listed below may be available for order. please contact atmel for availability details. notes: 1. consistent with the general semiconductor market trend, atmel will supply devices with either gold or copper bond wires to increase manufacturing flexibility and ensure a long-term continuity of supply. there is no difference in product quality, reliability, or performance between the two variations. 2. b = bulk delivery in tubes ? soic and tssop = 100 per tube 3. t = tape and reel ? soic = 4k per reel ? udfn and tssop = 5k per reel at34c04-ma5m-t atmel designator product family device density shipping carrier option device grade package option 04 = 4-kbit 34c = i 2 c-compatible serial presence detect (spd) serial eeprom b = bulk (tubes) t = tape and reel 5 = green, nipdau lead finish temperature range (-20c to +125c) ss = jedec soic x = tssop m = 1.7v to 3.6v voltage option ma = udfn ordering code (1) package lead finish voltage operational range at34c04-ss5m-b (2) 8s1 nipdau 1.7v to 3.6v ?20 ? c to 125 ? c at34c04-ss5m-t (3) at34c04-x5m-b (2) 8x at34c04-x5m-t (3) at34c04-ma5m-t (3) 8ma2 package type 8s1 8-lead, 0.150? wide body, plastic gull wing small outline (jedec soic) 8x 8-lead, 4.4mm body, plastic thin shrink small outline (tssop) 8ma2 8-pad, 2.0 x 3.0mm body, 0.5mm pitch, thermally enhanced plastic ultra thin dual flat no lead (udfn)
at34c04 [datasheet] atmel-8827d-seeprom-at34c04-datasheet_122013 26 12. package information 12.1 8s1 ? 8-lead jedec soic drawing no. rev. title gpc common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.05 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 ? ? 0 ? 8 ? e 1 n top view c e1 end view a b l a1 e d side view package drawing contact: packagedrawings@atmel.com 8s1 g 6/22/11 notes: this drawing is for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. 8s1, 8-lead (0.150? wide body), plastic gull wing small outline (jedec soic) swb
at34c04 [datasheet] atmel-8827d-seeprom-at34c04-datasheet_122013 27 12.2 8x ? 8-lead tssop drawing no. rev. title gpc common dimensions (unit of measure = mm) symbol min nom max note a - - 1.20 a1 0.05 - 0.15 a2 0.80 1.00 1.05 d 2.90 3.00 3.10 2, 5 e 6.40 bsc e1 4.30 4.40 4.50 3, 5 b 0.19 ? 0.30 4 e 0.65 bsc l 0.45 0.60 0.75 l1 1.00 ref c 0.09 - 0.20 side view end view top view a2 a l l1 d 1 e1 n b pin 1 indicator this corner e e notes: 1. this drawing is for general information only. refer to jedec drawing mo-153, variation aa, for proper dimensions, tolerances, datums, etc. 2. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exceed 0.15mm (0.006in) per side. 3. dimension e1 does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 0.25mm (0.010in) per side. 4. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius of the foot. minimum space between protrusion and adjacent lead is 0.07mm. 5. dimension d and e1 to be determined at datum plane h. package drawing contact: packagedrawings@atmel.com h 8x e 12/8/11 8x, 8-lead 4.4mm body, plastic thin shrink small outline package (tssop) tnr c a1
at34c04 [datasheet] atmel-8827d-seeprom-at34c04-datasheet_122013 28 12.3 8ma2 ? 8-pad udfn title drawing no. gpc rev. package drawing contact: packagedrawings@atmel.com 8ma2 ynz c 8ma2, 8-pad, 2 x 3 x 0.6 mm body, thermally enhanced plastic ultra thin dual flat no lead package (udfn) common dimensions (unit of measure = mm) symbol min nom max note d 1.90 2.00 2.10 e 2.90 3.00 3.10 d2 1.40 1.50 1.60 e2 1.20 1.30 1.40 a 0.50 0.55 0.60 a1 0.0 0.02 0.05 a2 ? ? 0.55 c 0.152 ref l 0.30 0.35 0.40 e 0.50 bsc b 0.18 0.25 0.30 3 k 0.20 ? ? 9/6/12 d2 e2 e e (6x) l (8x) b (8x) pin#1 id a a1 a2 pin 1 id d c k 8 7 6 5 1 2 3 4 1 2 3 4 8 7 6 5
at34c04 [datasheet] atmel-8827d-seeprom-at34c04-datasheet_122013 29 13. revision history doc. rev. date comments 8827d 12/2013 remove preliminary datasheet status. 8827c 07/2013 remove part number, at34c04-ma5m-b. update electrical specifications. update footers and disclaimer page. 8827b 12/2012 increase v por maximum from 1.5v to 1.6v. decrease t i 100khz maximum from 100ns to 50ns. minor changes to dc and ac characteristic tables. update datasheet status from advance to preliminary. 8827a 09/2012 initial document release.
x x x x x x atmel corporation 1600 technology drive, san jose, ca 95110 usa t: (+1)(408) 441.0311 f: (+1)(408) 436.4200 | www.atmel.com ? 2013 atmel corporation. all rights reserved. / rev.: atmel-8827d-seeprom-at34c04-datasheet_122013. atmel ? , atmel logo and combinations thereof, enabling unlimited possibilities ? , and others are registered trademarks or trademarks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others. disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in the atmel terms and condit ions of sales located on the atmel website, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its p roducts including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or incidental damages (including, without limi tation, damages for loss and profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or c ompleteness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. atmel d oes not make any commitment to update the information contained herein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automo tive applications. atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. safety-critical, military, and automotive applications disclaimer: atmel products are not designed for and will not be used in connection with any applications where the failure of such products would reasonably be expected to result in significant personal injury or death (?safety-critical a pplications?) without an atmel officer's specific written consent. safety-critical applications include, without limitation, life support devices and systems, equipment or systems for t he operation of nuclear facilities and weapons systems. atmel products are not designed nor intended for use in military or aerospace applications or environments unless specifically designated by atmel as military-grade. atmel products are not designed nor intended for use in automotive applications unless specifically designated by atmel as automotive-grade.

▲Up To Search▲

Price & Availability of AT34C04-14

	To Download AT34C04-14 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .